A conventional prior art inverting TTL tristate output device 10 is illustrated in FIG. 1. Data signals of high and low potential levels at the input V.sub.IN pass through an input circuit 12 including input transistor Q1 and a first stage of amplification provided by transistor element Q2 to the base of phase splitter transistor element QPS. Phase splitter QPS controls in opposite phase the conducting states of the pulldown transistor element QLOP and pullup transistor element provided by a Darlington transistor pair Q4 and Q5. The lower output pulldown transistor element QLOP sinks current from the output V.sub.OUT to low potential power rail GND. The pullup transistor Darlington Q4,Q5 sources current to the output V.sub.OUT from a high potential power rail V.sub.CC. Tristate circuit or OE signal input circuit 16 establishes the high impedance third state or tristate at the output V.sub.OUT.
Tristate circuit 16 includes an OE signal input and lines coupled to the respective base leads of the phase splitter QPS and pullup transistor Q5. Tristate circuit 16 therefore presents a high Z (impedance) at the output V.sub.OUT with a low potential level OE signal at the OE signal input.
Another tristate circuit 18 prevents current caused by voltage changes at the output V.sub.OUT feeding back through the internal Schottky diode clamp of pulldown transistor QLOP, from turning on QLOP during the high Z third state. This undesirable feedback current is referred to as "Miller current". A Miller killer transistor element QMK is coupled with collector and emitter nodes between the base lead of lower output pulldown transistor QLOP and the low potential power rail GND. Tristate circuit 18 includes a DCMK signal input coupled to the base of the Miller killer transistor element QMK through ballast resistor RB for turning on QMK when a high potential level DCMK signal appears at the DCMK signal input.
A high potential DCMK signal turns on the Miller killer transistor element QMK discharging the base of QLOP and any Miller current fed back to the base node of QLOP by fluctuations at the output V.sub.OUT. The output V.sub.OUT may be tied to a common bus. A low potential DCMK signal turns off QMK and enables the normal bistate mode of operation of the output device.
The ballast resistor RB is intended to suppress current hogging between multiple QMK's coupled in parallel for multi-bit line drivers such as hex and octal line drivers incorporating multiple TTL tristate output buffers of the type illustrated in FIG. 1. The DCMK signal input may be coupled to multiple QMK's of the multiple output buffers through respective ballast resistors as hereafter described.
The DC Miller killer DCMK signal is out of phase with the OE signal and in phase with the complementary OE signal. The OE signal and DCMK signal are derived through double gate inversion as shown in FIG. 2. A first stage output enable OE inverting buffer circuit IB1 receives a complementary OE signal at an OE signal input and provides an OE signal output coupled to the OE signal input of tristate circuit 16. A second stage enable signal inverting buffer IB2 provides the DCMK signal output coupled to the DCMK signal input of tristate circuit 18. The DCMK signal output is in phase with the OE signal input and is coupled to the base node of QMK through ballast resistor RB.
In the Farhad Vazehgoo U.S. Pat. No. 4,649,297 issued Mar. 10, 1987, a prior art TTL tristate output device similar to FIG. 1 herein is illustrated in FIG. 5 of that patent. In the Vazehgoo FIG. 5 circuit the output enable OE signal is designated "E" and the complementary DCMK signal is designated "A". In FIG. 6 of U.S. Pat. No. 4,649,297, Vazehgoo suggests deriving the DCMK or "A" signal from an emitter follower transistor element coupled directly to the OE or "E" signal input circuit for avoiding the double inversion coupling sequence and accompanying signal propagation delay. However, Vazehgoo does not address the current hogging problem of multiple Miller killer transistor elements QMK encountered in multi-bit line drivers with multiple TTL tristate output devices coupled in parallel. Nor does he suggest how such a circuit to avoid QMK current hogging might be configured and implemented in this context. The problem of QMK current hogging in TTL tristate output multi-bit line drivers is summarized as follows.
A prior art circuit for TTL tristate output multi-bit line drivers such as hex or octal line drivers is illustrated in FIG. 3. A separate output buffer of the type illustrated in FIG. 1 is provided for each output bit of the multi-bit line driver. A fragmentary portion of these multiple output buffers is shown in FIG. 3 including the data bit outputs BIT0...BITn, pulldown transistor elements QLOP0...QLOPn, and ballast resistors RB0...RBn.
OE and DCMK signals for all of the multiple output buffers are generated by enable inverting buffer stages IB1 and IB2 as in FIG. 2. The DCMK signal output from IB2 is coupled in parallel to the respective ballast resistors RB0...RBn for Miller killer transistor elements QMK0...QMKn. The ballast resistors RB0...RBn are intended to reduce current hogging between the respective QMK's for effective discharge of base current from the respective QLOP's of the different bit output buffers. A fragmentary portion of the output circuit of IB2 shows the coupling of the output of IB2 between IB2 pulldown transistor QA and pullup resistor RA to the ballast resistors RB0...RBn.
Further description of prior art DC Miller killer circuits can be found in the Ferris et al. U.S. Pat. No. 4,581,550 issued Apr. 8, 1986; the Ferris U.S. Pat. No. 4,311,927 issued Jan. 19, 1982; and the Hannington U.S. Pat. No. 4,677,320 issued June 30, 1987.
One disadvantage of prior art lower output pulldown tristate circuits or DC Miller killer circuits noted above is that two inverting stages, IB1 and IB2, are conventionally used to generate the DCMK signal introducing tristate switching delays for the tpZL and tpLZ transitions. The propagation times or switching times for switching between a high Z tristate signal and a low potential data signal at the output are designated tpZL and tpLZ.
A further disadvantage is that for multi-bit line driver applications, the ballast resistors do not effectively prevent current hogging between the multiple QMK's. Where the QMK's are required to sink differing collector currents for discharging the bases of the respective QLOP's, current hogging may prevent a QMK from sinking a larger required collector current. The ballast resistors may also have large resistance, further slowing the switching speed of the QMK's.